Notice bibliographique
- Notice
Type(s) de contenu et mode(s) de consultation : Texte noté : électronique
Auteur(s) : VDAT Symposium (17 ; 2013 ; Jaipur, India)
Titre(s) : VLSI design and test [Texte électronique] : 17th International Symposium, VDAT 2013, Jaipur, India, July 27-30, 2013, revised selected papers / Manoj Singh Gaur [and others] (eds.)
Publication : Heidelberg : Springer, cop. 2013
Description matérielle : 1 online resource (xvi, 388 pages)
Collection : Communications in computer and information science ; 382
Note(s) : Includes bibliographical references and index
This book constitutes the refereed proceedings of the 17th International Symposium
on VLSI Design and Test, VDAT 2013, held in Jaipur, India, in July 2013. The 44 papers
presented were carefully reviewed and selected from 162 submissions. The papers discuss
the frontiers of design and test of VLSI components, circuits and systems. They are
organized in topical sections on VLSI design, testing and verification, embedded systems,
emerging technology
Autre(s) auteur(s) : Gaur, Manoj Singh. Fonction indéterminée
Autre(s) forme(s) du titre :
- Autre forme du titre : VDAT 2013
Sujet(s) : Informatique
Microtechniques
Ordinateurs
Indice(s) Dewey :
621.395 (23e éd.) = Systèmes de circuits (génie informatique) ; 004 (23e éd.) = Informatique
Identifiants, prix et caractéristiques : ISBN 9783642420245
Identifiant de la notice : ark:/12148/cb447082748
Notice n° :
FRBNF44708274
(notice reprise d'un réservoir extérieur)
Table des matières : VLSI design ; Testing and verification ; Embedded systems ; Emerging technology.
Process Aware Ultra-High-Speed Hybrid Sensing Technique for Low Power Near-Threshold
SRAM /Bhupendra Singh Reniwal, Santosh Kumar Vishvakarma ; A Novel Design Methodology
for High Tuning Linearity and Wide Tuning Range Ring Voltage Controlled Oscillator
/Gudlavalleti Rajahari, Yashu Anand Varshney, Subash Chandra Bose ; A Low-Power Wideband
High Dynamic Range Single-Stage Variable Gain Amplifier /Vivek Verma, Chetan D. Parikh
; An Ultra-Wideband Baseband Transmitter Design for Wireless Body Area Network /R.K.
Naga Mahesh, Akash Ganesan, Manchi Pavan Kumar, Roy Paily ; Computational Functions'
VLSI Implementation for Compressed Sensing /Shrirang Korde, Amol Khandare, Raghavendra
Deshmukh, Rajendra Patrikar ; A Novel Input Capacitance Modeling Methodology for Nano-Scale
VLSI Standard Cell Library Characterization /Akhtar W. Alam, Esakkimuthu Dhakshinamoorthy,
Prince Mathew, Narender Ponna
An Area Efficient Wide Range On-Chip Delay Measurement Architecture /Rahul Krishnamurthy,
G.K. Sharma ; 10 Gbps Current Mode Logic I/O Buffer /Akhil Rathore, Chetan D Parikh
; Kapees: A New Tool for Standard Cell Placement /Sameer Pawanekar, Kalpesh Kapoor,
Gaurav Trivedi ; Preemptive Test Scheduling for Network-on-Chip Using Particle Swarm
Optimization /Kanchan Manna, Shailesh Singh, Santanu Chattopadhyay, Indranil Sengupta
; Energy Efficient Array Initialization Using Loop Unrolling with Partial Gray Code
Sequence /Sumanta Pyne, Ajit Pal ; Design and Simulation of Bulk Micromachined Accelerometer
for Avionics Application /Amit Sharma, Ravindra Mukhiya, S. Santosh Kumar, B.D. Pant
; Performance Analysis of Subthreshold 32-Bit Kogge-Stone Adder for Worst-Case-Delay
and Power in Sub-micron Technology /Himadri Singh Raghav, Sachin Maheshwari, B. Prasad
Singh
Characterization of Logical Effort for Improved Delay /Sachin Maheshwari, Himadri
Singh Raghav, Anu Gupta ; A Dual Material Double-Layer Gate Stack Junctionless Transistor
for Enhanced Analog Performance /Ratul Kumar Baruah, Roy P. Paily ; An Improved g
m /I D Methodology for Ultra-Low-Power Nano-Scale CMOS OTA Design /Somnath Paul, Abhijit
Dana, Soumya Pandit ; An Efficient RF Energy Harvester with Tuned Matching Circuit
/Sachin Agrawal, Sunil Pandey, Jawar Singh, P.N. Kondekar ; A Modified Gate Replacement
Algorithm for Leakage Reduction Using Dual-Tox in CMOS VLSI Circuits /Surabhi Singh,
Brajesh K. Kaushik, Sudeb Dasgupta ; Impact of Fin Width and Graded Channel Doping
on the Performance of 22nm SOI FinFET /Jose Joseph, Rajendra Patrikar ; Power Reduction
by Integrated Within_Clock_Power Gating and Power Gating (WCPG_in_PG) /Debanjali Nath,
Priyanka Choudhury, Sambhu Nath Pradhan
Design and Analysis of a Novel Noise Cancelling Topology for Common Gate UWB LNAs
/Mohd Anwar, Syed Azeemuddin, Mohammed Zafar Ali Khan ; A Combined CMOS Reference
Circuit with Supply and Temperature Compensation /Madhusoodan Agrawal, Alpana Agarwal
; Convex Optimization of Energy and Delay Using Logical Effort Method in Deep Sub-micron
Technology /Sachin Maheshwari, Rameez Raza, Pramod Kumar, Anu Gupta ; A Cache-Aware
Strategy for H.264 Decoding on Multi-processor Architectures /Arani Bhattacharya,
Ansuman Banerjee, Susmita Sur-Kolay [and others] ; Random-LRU: A Replacement Policy
for Chip Multiprocessors /Shirshendu Das, Nagaraju Polavarapu, Prateek D. Halwe, Hemangee
K. Kapoor ; Analysis of Crosstalk Deviation for Bundled MWCNT with Process Induced
Height and Width Variations /Jainender Kumar, Manoj Kumar Majumder, Brajesh Kumar
Kaushik, Sudeb Dasgupta ; Congestion Balancing Global Router /Shyamapada Mukherjee,
Jibesh Patra, Suchismita Roy
CMOS ASIC Design of a High Performance Digital Fuzzy Processor That Can Compute on
Arbitrary Membership Functions /Anirban Guha, Shubhajit Roy Chowdhury ; Variation
Robust Subthreshold SRAM Design with Ultra Low Power Consumption /Saima Cherukat,
Vineet Sahula ; Modeling of High Frequency Out-of-Plane Single Axis MEMS Capacitive
Accelerometer /Prashant Singh, Pooja Srivastava, Ram Mohan Verma, Saurabh Jaiswal
; CPK Based IO AC Timing Closure to Reduce Yield Loss and Test Time /Sandip Ghosh,
Rohit Srivastava ; Optimization of Underlap FinFETs and Its SRAM Performance Projections
Using High-k Spacers /Pankaj Kr. Pal, Brajesh Kumar Kaushik, Sudeb Dasgupta ; On-Chip
Dilution from Multiple Concentrations of a Sample Fluid Using Digital Microfluidics
/Sudip Roy, Bhargab B. Bhattacharya, Sarmishtha Ghoshal, Krishnendu Chakrabarty
Automatic Test Bench Generation and Connection in Modern Verification Environments:
Methodology and Tool /Rohit Srivastava, Gaurav Gupta, Sarvesh Patankar, Nandini Mudgil
; A Methodology for Early and Accurate Analysis of Inrush and Latency Tradeoffs during
Power-Domain Wakeup /Vipul Singhal, Ayon Dey, Suresh Mallala, Somshubhra Paul ; Fault
Aware Dynamic Adaptive Routing Using LBDR /Rimpy Bishnoi, Vijay Laxmi, Manoj Singh
Gaur, Mohit Baskota ; Architectural Level Sub-threshold Leakage Power Estimation of
SRAM Arrays with its Peripherals /Nupur Navlakha, Lokesh Garg, Dharmendar Boolchandani,
Vineet Sahula ; On Designing Testable Reversible Circuits Using Gate Duplication /Joyati
Mondal, Debesh Kumar Das, Dipak Kole, Hafizur Rahaman, Bhargab B. Bhattacharya
Circuit Transient Analysis Using State Space Equations /Kai Chi Alex Lam, Mark Zwolinski
; 3D CORDIC Algorithm Based Cartesian to Spherical Coordinate Converter /Anita Jain,
Kavita Khare ; Level-Accurate Peak Activity Estimation in Combinational Circuit Using
BILP /Jaynarayan T. Tudu, Deepak Malani, Virendra Singh ; Design and Optimization
of a 2x2 Directional Microstrip Patch Antenna /Cerin Ninan, Chandra Shekhar, M. Radhakrishna
; A New Method for Route Based Synthesis and Placement in Digital Microfluidic Biochips
/Pranab Roy, Samadrita Bhattacharya, Hafizur Rahaman, Parthasarathi Dasgupta ; Defect
Diagnosis of Digital Circuits Using Surrogate Faults /Chidambaram Alagappan, Vishwani
D. Agrawal
